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1 GLT41016-10E 64k x 16 embedded edo dram f eatures u logical organization: 64k x 16 bits u physical organization: 256 x 256 x 16 u single 3.3v 0.3v power supply u 256 cycle refresh in 4 ms u refresh modes: ras only, cbr, and hidden u dual cas for byte write and byte read control u separate i/o operation u 100 mhz page mode edo cycle u 30 ns row access time u redundancy: 2 wl/256k, 2 cs/1m g eneral d escription the 1 mbit embedded dram (emdram) is an asynchro- nous design with non-multiplexed row and column addressing scheme. the memory operations are con- trolled by ras , cash /casl , and we . byte access is controlled by cash (upper byte) and casl (lower byte). the emdram has been designed to support 200mbyte data rate with a 30 ns latency when operated in the page mode with extended data output (edo). this maximum rate can be sustained for one page of 12 bytes. performance data parameter -30 max. ras access time, t rac 30 ns max. column address access time, t aa 12 ns max. cas access time, t cac 8 ns min. extended data out page mode cycle time, t pc 10 ns min. read/write cycle time, t rc 60 ns may 1997 (rev. 1)
2 g-link technology GLT41016-10E may 1997 (rev. 1) f unctional b lock d iagram 1. on-chip power supply to the emdram should be separated from the logic portion. ras timing generator lcas column address buffers internal address counter row address buffers refresh control clock column decoders sense amps memory cells word drivers row decoders a[8:0] i/o selector output buffer input buffer dq[15:8] v ss v cc output buffer input buffer dq[7:0] ucas i/o controller i/o controller we oe figure 1. glt44016 - 256k x 16 y[8:0] x[8:0] signal descriptions [1] symbol type description di[15:0] input data in. do[15:0] output data out. xra[7:0] input row address. xca[7:0] input column address. ras input row address strobe (active low). cash input column address strobe, access di/do[15:8] (active low) casl input column address strobe, access di/do[7:0] (active low) we input write enable (active low). oe input output enable (active low). v dd supply 3.3v voltage supply, 2 pairs double bond minimum v ss supply ground (voltage return), 2 pairs double bond minimum
3 g-link technology GLT41016-10E may 1997 (rev. 1) function table input pin dq pin functional mode ras lcas ucas we oe dq[7:0] dq[15:8] h high-z high-z standby l h h high-z high-z refresh llhhl d out high-z lower byte read lhlhl high-z dout upper byte read l l l h l dout dout word read llhlh din don? care lower byte write l h l l h don? care din upper byte write llllh din din word write l l l h h high-z high z truth table function ras cas we oe address dqm0 dqm1 dqm2 dqm3 di[31:0] do[31:0] standby h h x x x xxxx x high-z read l l h l row/col xxxx x data out write (early) l l l x row/col hhhh data in high-z write di[7:0] l l l x row/col l h h h data in high-z write di[15:8] l l l x row/col h l h h data in high-z write di[23:16] l l l x row/col h h l h data in high-z write di[31:24] l l l x row/col h h h l data in high-z read-write l l h ? ll ? h row/col hhhh data in data out page-mode read (first cycle) l h ? l h l row/col xxxx x data out page-mode read (subsequent cycles) h ? lhlcol xxxx x data out page-mode write (first cycle) l h ? l l x row/col hhhh data in high-z page-mode write (subsequent cycle) l h ? llxcol hhhh data in high-z page-mode r-w (first cycle) l h ? lh ? ll ? h row/col hhhh data in data out page-mode r-w (subsequent cycle) l h ? lh ? ll ? hcol hhhh data in data out cbr refresh h ? llxx x xxxx x high-z ras-only refresh l h x x row xxxx x high-z
4 g-link technology GLT41016-10E may 1997 (rev. 1) e lectrical s pecifications 1. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1. i cc max. is specified for i cc for the output open condition. 2. address can be changed once or less while ras = v il . 3. address can be changed once or less while cas = v ih . absolute maximum ratings [1] symbol parameter conditions value unit v t voltage on any pin relative to v ss t a = 25 ?c -0.5 to +4.6 v i os short circuit output current t a = 25 ?c 50 ma p d power dissipation t a = 25 ?c 1 w t opr operating temperature 0 to +70 c t stg storage temperature -55 to +150 c recommended operating conditions (t a = 0 c to +70 c) symbol parameter min typ max unit v cc power supply voltage 3.0 3.3 3.6 v v ss 000v v ih input high voltage 2.4 v cc +1 v v il input low voltage -1.0 0.8 v capacitance (v cc = 5v 10%, t a = 25 c, f = 1 mhz) symbol parameter min typ max unit c in1 input capacitance (a[8:0]) 1 pf c in2 input capacitance (ras , lcas , ucas , we , oe )1pf c i/o input/output capacitance (dq[15:0]) 1 pf dc characteristics (v cc = 5v 10%, t a = 0 c to +70 c) symbol parameter condition -30 units note min max v oh output high voltage i oh = -2 ma 2.4 v cc v v ol output low voltage i ol = -1.0ma 0 0.4 v i li input leakage current 0v v in v cc -2 -2 m a i lo output leakage current dqi disable 0v v o 3.6v -10 -10 m a i cc1 average power supply current (operating) ras , cas cycling, t rc =min. 200 ma [1] [2] i cc2 power supply current (standby) ras , cas = v ih ma [1] i cc3 average power supply current (ras-only refresh) ras -cycling, cas = v ih, t rc = min. 200 ma [1] [2] i cc4 average power supply current (fast page mode) ras = v il, cas cycling, t hcp = min. 140 ma [1] [3] i cc5 average power supply current (cas -before-ras refresh) ras cycling, cas -before-ras 200 ma
5 g-link technology GLT41016-10E may 1997 (rev. 1) 1. maximum cash to casl skew is 1 ns. 2. last casx low. 3. last casx high. 4. first casx low. 5. first casx high. 6. last casx low to first casx high. 7. last casx high to first casx low. ac characteristics (v cc = 3.3 v 10%, t a = 0 c - 70 c, c l = 1 pf) symbol description min max units notes t rc random read/write cycle time 60 ns t pc page mode read/write cycle 10 ns [1] [2] t off read data valid from ras high 0 ns [3] t doh read data valid from next cas low 3 ns [4] t aa access time from column address 12 ns t rac access time from ras low 30 ns t cac access time from cas low 8 ns [2] t cpa access time from cas precharge 14 ns [3] t ras ras pulse width 30 ns t rcd ras to cas delay time 15 35 ns t csh cas hold time for ras 30 [5] t cas cas pulse width 4 ns [6] t asr row address setup time 3 ns t rah row address hold time 3 ns t asc column address setup time 3 ns [4] t cah column address hold time 3 ns [2] t cp cas precharge time 4 ns [7] t ds write data setup time 3 ns [4] t dh write data hold time 3 ns [2] t rp ras precharge time 20 ns t crp cas to ras precharge time 15 ns [3] t rsh cas low to ras high hold time 10 ns [2] t rcs read command setup time 0 ns [4] t rch read command hold time from cas high 0 ns [3] t rrh read command hold time from ras high 0 ns t wcs write command setup time 5 ns t wch write command hold time 5 ns t wp we pulse width 8 ns t t transition time (rise and fall) 1.5 ns t rwl write command to ras high 8 ns t cwl write command to cas high 8 ns [5]
6 g-link technology GLT41016-10E may 1997 (rev. 1) figure 2. read cycle (ras output control) don? care ras t rc t ras t rp t rsh t cas t rcd t crp lcas , ucas t ar t ral t rad t cah t rah t asr t asc a[8:0] we oe dq t csh t rcs t aa t rrh t rch t oea t roh t cac t oez t off t rac hi-z row column valid data figure 3. read cycle (cas output control) don? care ras t rc t ras t rp t rsh t cas t rcd t crp lcas , ucas t ar t ral t rad t cah t rah t asr t asc a[8:0] we oe dq t csh t rcs t aa t rrh t oea t roh t cac t oez t off t rac hi-z valid data row column
7 g-link technology GLT41016-10E may 1997 (rev. 1) figure 4. early write (lcas and ucas active) don? care ras t rc t ras t rp t rsh t cas t rcd t crp lcas , ucas t ar t ral t rad t cah t rah t asr t asc a[8:0] we oe dq t csh t wp t wsc t wch t wcr t cwl t rwl t ds t dh t dhr hi-z valid data column row ras figure 5. late write (lcas and ucas active) t rc t ras t rp t rsh t cas t rcd t crp lcas , ucas t ar t ral t rad t cah t rah t asr t asc t cwl t rwl t wp t rcs t wcr t oeh t dh t ds a[8:0] we oe dq t csh don? care row column valid data
8 g-link technology GLT41016-10E may 1997 (rev. 1) ras figure 6. read modify write cycle (lcas and ucas active) t rmw t ras t rp t csh t rsh t cas t rcd t crp lcas , ucas t ar t ral t rad t cah t rah t asr t asc t rcs a[8:0] we t awd t cwl t rwl t wp t oeh t rwd t cwd t dzo t oea t oez t ds t dh t dzc t cac t oed t rac dq oe don? care row column out in figure 7. fast page mode read cycle with extended data out ras t rc t rasp t crp t rcd t cas t cp t cas t cp t cas t csh t pc t rsh t rp t asr t rah t asc t cah t asc t cah t asc t cah t rad t ral t ar t rcs t rch t rrh t oea t cac t aa hz t cac t coh t cac t coh t oez t rez t rac t cpa t aa t aa lcas , ucas a[8:0] we oe dq t cpa don? care row column column column valid data valid data valid data
9 g-link technology GLT41016-10E may 1997 (rev. 1) valid data t oea t oez t rch t rcs t cp t asc ras figure 8. fast page mode read hi-z operation lcas , ucas t crp t rasp t rc t rp t csh t ar t rcd t cas t hpc t cas t cp t cas t cp t cas t rsh t crp t rad t cah t cah t cah t cah t ral t rah t asr t asc t asc t asc t rcs t rch t rrh t wep t rac t cho t och t oep t oep t cac t cac t aa t cac t cpa t aa t cac t aa t coh t oez t oea t oea t wez t aa t rez we oe dq a[8:0] don? care row column valid data column column column valid data valid data valid data figure 9. fast page mode early write cycle ras t rc t rasp t crp t rcd t cas t cp t cas t cp t cas t csh t pc t rsh t rp t asr t rah t asc t cah t asc t cah t asc t cah t rad t ral t ar lcas , ucas a[8:0] we oe dq t cwl t wcs t wch t cwl t wcs t wp t wch t wcs t wp t wch t cwl t ds t dh t ds t dh t ds t dh t wp don? care row column column column input data input data input data
10 g-link technology GLT41016-10E may 1997 (rev. 1) t asc t cwl t cwl figure 10. fast page mode read modify write cycle ras t rc t rasp t crp t rcd t cas t cp t rp t asr t ral t ar a[8:0] we oe dq t cp t csh t rsh t cas t cas t prmw t rah t asc t asc t cah t cah t rad t cah t awd t wp t cwd t rcs t wp t awd t cwd t wp t cwl t awd t cwd t oea t oez t oea t oez t oea t oez t aa t ds t cac t dh t aa t cac t ds t dh t cac t aa t ds t dh don? care lcas , ucas row column column column out out out in in in figure 11. cas -before-ras refresh cycle ras a[8:0] we oe dq t rc t ras t rp t rp t rpc t csr t chr t rpc t off hz inhibit falling transition don? care lcas , ucas
11 g-link technology GLT41016-10E may 1997 (rev. 1) figure 12. hidden refresh cycle ras t rc t rp t ar a[8:0] we oe dq t ras t ras t crp t rcd t chr t asr t rah t asc t cah t rad t ral t rsh t rrh t oea t roh t oez t aa t cac t rac hz t off t rcs lcas , ucas don? care row column valid data figure 13. ras -only refresh cycle don? care ras t rc t ras t rp t crp lcas , ucas t rah t asr a[8:0] dq hi-z t rpc we , oe row
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